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GLOSSARY
OF TERMS |
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PC 100
The list below gives an overview of three PC SDRAM (PC-100) specifications as defined by Intel. Taken together the specifications define the PC-100 DIMM’s.
- PC SDRAM Unbuffered DIMM specification (Revision 1.0, February 1998): This specification is the guideline for the DIMM design. This specification goes beyond the JEDEC mechanical form factor and pin out requirement. This specification defines the connections, component placements trace impedance, signal topologies and trace length requirements for designing and manufacturing PC-100 DIMMS.
- PC SDRAM Specification (Version 1.51, November 1997): This specification defines the essential functionality of the SDRAM components to be used on the PC-100 DIMM’s.
- PC SDRAM Serial Presence Detect (SPD) Specification (Revision 1.2A, December 1997): This specification defines the SPD electrical and Data Structure requirements for SDRAM DIMM’s.
SDRAM |
Synchronous Dynamic Memory
Memory chips that synchronize the signal input and output with the CPU clock. This results in time saving thus improving performance. Execution of commands and transmission of data is in sync with CPU clock.
Althou the SDRAM’s are designed to JEDEC standard, slight differences in the interpretation of the specification and the test methodologies have made the interchangeability a concern. Chips were capable of 100 MHz system operation under ideal conditions, but due to timing differences in most PC’s they have limited operation to 66MHz.
New PC100 SDRAM chips are designed to increase performance and comply with tightened ac timing margins, dc parameters, driver characteristics and layout rules. (See above INTEL PC100 specifications).
Available in two and four internal memory banks per chip. The chips operate at 3.3V. Currently capable of up to 143MHz/sec bandwidth. |
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DDRAM |
Double Data Random Access Memory |
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Essentially doubles the data transfer rate from a DRAM chip to the main processor. This is one of the new standards that are supported by following manufacturers: Samsung, NEC, Hyundai, Texas Instruments, Toshiba, Mitsubishi, Hitachi and Fujitsu.
Currently this new, DDR standard manufactured chips are considered an interim before actual implementation of RamBUS high-speed memory.
The chips will operate at 3.3V. Capable of 200MHz/sec bandwidth.
DDR DRAM has, with their design stages, advanced to the later stage of JEDEC committee approval process. Final standardization of DDR specification is expected soon.
Because of its open architecture, similar pin-out and packaging the incorporation into memory module requires few changes. |
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SLDRAM |
SyncLink
Similar to SDRAM, but has eight internal memory banks. Uses both the rising and falling clock edge to transmit data and a return clock signal to help improve timing margins. Main supporters include Siemens Micron and Hyundai. The chips will operate at 2.5V. Capable of up to 800MHz/sec bandwidth. SLDRAM has received JEDEC approval for its packaging pinout specification and should appear for full committee vote later this year. |
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Because of its open architecture, similar pin-out and packaging the incorporation into memory module requires few changes.
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MDRAM |
Multibank DRAM
Internally uses 32 banks per megabyte. Will permit the chips to handle many overlapping transactions, thus maximizing the data bandwidth. One limitation is that they require short buses and that in turn, limits the number of memory chips to four. Somewhat limited for memory applications. Capable of up to 600MHz/sec.
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RDRAM |
RamBUS,
Concurrent RamBUS , version of RDRAM is divided into four banks (two banks on the 16/18-bit version). This is the second-generation implementation that has many timing and feature improvements over RDRAM. New memory architecture capable of 600MHz.
Direct RamBUS, version of RDRAM. Jointly developed by INTEL to better match the memory to the Pentium CPU and deliver roughly 3 times the effective bandwidth of SDRAM. Licensees that will produce the chips are Hitachi, LG Semicon, NEC, Toshiba, OKI, Fujitsu, Hyundai, Siemens, IBM, Texas Instruments, Micron, Mitsubishi…..
This will be the first of the super-pipelined memories that offer multiple-transaction pipeline and conflict-free transaction interleaving to achieve a sustained performance of 800MHz/sec. Chips will be controlled by RamBUS access controller (RAC) which can support single DRDRAM interface or two Concurrent RDRAM interfaces. Chips will operate at 2.5V.
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PEMM |
Processor Enable Memory Module
New variations on the memory module design implementing DSP processors. Developed by Texas Instruments and code named Basaya the module will work with Pentium II and have 168 pin and 144 pin DIMM module pin-out. The module performs as regular SDRAM module until a DSP call comes in. At that point a dedicated partition is established in the memory function which, since it circumvents the slower PCI bus, performs radically better than traditional architectures. |
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Comparison of Next-Generation of 64-Mbit DRAM’s |
Parameter / Type |
SDRAM |
DDRAM |
SLDRAM |
Direct RAMBUS |
Bandwidth |
0.8 Gbytes/s |
1.6Gbytes/s |
1.6Gbytes/s |
1.6Gbytes/s |
Clock Frequency |
100MHz |
100MHz |
200MHz |
400MHz |
Data-Transfer Frequency |
100MHz |
200MHz |
400MHz |
800MHz |
Package |
TSOP/DIMM |
TSOP/DIMM |
VSMP/DIMM |
TBD |
Application |
Low end-high end |
Midrange-high end |
Midrange-high end |
Low end-midrange |
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